1. Field of the Invention
This invention relates to the field of memory arrays within integrated circuits. More particularly, this invention relates to the repair of defective circuits within memory arrays.
2. Description of the Prior Art
It is know to provide memory arrays with repair circuits which seek compensate for defective circuit elements within those memory arrays. As an example, it is known to provide redundant column and redundant row circuitry whereby, if a column or a row is defective, then it can be functionally substituted with a redundant column or a redundant row. Whilst these techniques are effective in improving the yield of useable integrated circuits, they suffer from the disadvantage of requiring additional circuit area overhead to provide the redundant columns and rows. Furthermore, a finite number such redundant columns may be provided and, if the number of defective rows or columns exceeds the number of redundant rows or columns, then repair then cannot be made and the integrated circuit cannot be used.
As process geometry is falling in size, the vulnerability of circuit elements within memory arrays to defects in their manufacture increases. As an example, the SRAM bits cell current on-to-off ratio has been decreasing rapidly as processed technology decreases in size. This reduction in the on-to-off ratio is primarily the result of sub-threshold leakage or “off” current of transistors used within such bit cells becoming a significant fraction of the “on” current due to what are commonly known as “short-channel” effects. Furthermore, the bit cell “on” current is not increasing in line with the historical scaling trends due to many reasons, including scaling limitations of gate oxide and threshold voltage. In addition, the increased significance of two dimensional electric field effects and other effects relating to the physics of operation of small scale circuit elements further increase the “off” current due to phenomenon such as gate tunneling and band-to-band tunneling which make the ratio of the on-to-off current even worse. As a consequence of the above factors, a bit cell being read might not be able to provide sufficient current for the bit line pair to develop a sufficient voltage differential during the time period required for sensing the stored data value. This would result in either an error in the state being read or the speed requirements for the memory not being met. If there is a large number of such bit cells within a single block of memory beyond the number that can be repaired by traditional redundancy techniques, then the integrated circuit will have to be discarded. It should be noted that the traditional redundancy schemes, and particularly redundant rows, have a significant area and timing overhead. In addition, they are ill suited to repairing for drifts in process parameters, weak or erratic bits or defects of a gross nature.
One approach to the above would be to design the memory arrays with a significant margin to cover expected process variations. However, as the process scales to smaller geometries, acceptable levels of margin in the design still result in a significant number of integrated circuits being produced which have errors beyond those which can be repaired by traditional row and column redundancy techniques. This problem is likely to become more severe as the geometries scale to smaller sizes.